Supplying power to integrated circuits such that there is a relatively constant voltage supplied across different devices that will have different impedances and different power requirements is not straightforward. Time varying circuit impedance and imperfect voltage regulation can both lead to supply voltage swings. Changes in the voltage difference seen by devices is of concern as it limits their performance and power efficiency and may even lead to failure in a functional device. In particular, large fast digital circuits in deep sub-micron process technologies are susceptible to supply voltage droop and therefore require extra development effort to ensure the power delivery network and the chip package are suitably tuned. Furthermore, with modern techniques of aggressive clock gating and with ever increasing power density this problem is becoming exasperated.
It may therefore be advantageous to detect supply voltage noise on-chip in order to detect unsatisfactory operating conditions. Detecting the supply grid off-chip may not provide a suitable measurement as there may be local droop due to changes in impedance or particular high power requirements of nearby devices. Detecting the supply voltage noise can be used either to help control the performance of the circuit by adjusting the voltage, the clocking frequency or functional operation of the circuit in response to detecting noise on the supply voltage, or it can be used when testing or debugging the circuit. In this regard supply voltage swing presents a tricky problem for test. BIST and scan test patterns are in no way guaranteed to replicate similar supply voltage droop events to functional test. In fact, since scan patterns are traditionally designed to exercise as much of the IC in as little time as possible, they often present a fairly constant, high current draw. This generally means that extra margin is required on supply voltage in order to prevent test escape.
It may however, be difficult to accurately detect supply voltage levels at different points within an integrated circuit. In particular, it may be difficult both to generate a suitable DC reference voltage as a comparison voltage and to implement a fast, low power and area comparator that is reasonably accurate. Generally such circuits are analogue in design and require large well matched transistors. This makes it difficult to add such monitoring circuit to areas of high cell density which are often the areas where fast voltage droop occurs. In particular, where the monitoring circuits are large, adding these circuits requires other cells to be moved further apart and may therefore increase wiring loading and effectively make the problem worse.
In summary on-chip supply noise is an increasingly important problem that can lead to over-margining to prevent test escapes. Monitoring noise on-chip is attractive to allow extra dynamic margin to be introduced adaptively, in adverse conditions. Detecting local supply noise at low power and area overhead is a significant challenge.
It would be advantageous to be able to monitor supply voltage levels within a circuit accurately in areas of high cell density and without increasing the power and area requirements of the circuit unduly.